Design Verification Engineer- IP Verification

Hiring for

Techwurkz Client for its customer who is one of the largest global professional services into management consulting, tax, audit, advisory and other services

Company Description

US based IT services and workforce solutions company operating globally

Role Description

Design verification engineer with strong experience in IP verification

Qualifying experience

• Extensive experience in executing IP verification or subsystem verification of complex blocks or SOC verification. 
• Excellent in System Verilog (SV), Universal Verification Methodology (UVM), test bench component development, assertions, testbenches, test plans, and coverage. 
• Strong experience in verifying Fabric/NOC/Interconnect blocks. 
• Knowledge of protocols such as AMBA suite (AXI/ACE), PCIe, CXL, interrupt handling, and power management. 
• Experience or knowledge of coherent traffic verification is a plus. 
• Specific requirement – total experience (5+ years) with SOC GLS experience of 3+ years (Zero Delay, SDF, PA GLS, debugging failures and fixing issues) – Open Position 2 (Immediate – only CG interview, no customer interview) 
• Specific requirement – total experience 4-5 years; SV/UVM, IP/SS/SOC Verification, GLS experience of 2+ years (Zero Delay, SDF, PA GLS, debugging failures and fixing issues) – Open Position 3 (with customer interview) 
• Specific requirement 5–7 years of ARM-based SoC verification experience. Strong debug skills with AXI/AHB/APB, memory, and NoC components. Proficiency in SystemVerilog, UVM, and C/C++ modeling. 
• Specific requirement Strong SV, UVM, Test Bench (components), PCIe, 5+ years